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SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications rev. 01 12 july 2004 objective data 1. description the SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 con?gurable registered buffer designed for 1.7 v to 1.9 v v dd operation. all clock and data inputs are compatible with the jedec standard to sstl_18. the control inputs are lvcmos. all outputs are 1.8 v cmos drivers that have been optimized to drive the ddr2 dimm load. the SSTU32864 operates from a differential clock (ck and ck). data are registered at the crossing of ck going high, and ck going low. the c0 input controls the pinout con?guration of the 1:2 pinout from a con?guration (when low) to b con?guration (when high). the c1 input controls the pinout con?guration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). the device supports low-power standby operation. when the reset input ( reset) is low, the differential input receivers are disabled, and undriven (?oating) data, clock and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs are forced low. the lvcmos reset and cn inputs must always be held at a valid logic high or low level. to ensure de?ned outputs from the register before a stable clock has been supplied, reset must be held in the low state during power-up. in the ddr2 rdimm application, reset is speci?ed to be completely asynchronous with respect to ck and ck. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs will remain low, thus ensuring no glitches on the output. the device monitors both d cs and csr inputs and will gate the qn outputs from changing states when both d cs and csr inputs are high. if either d cs or csr input is low, the qn outputs will function normally. the reset input has priority over the d cs and csr control and will force the outputs low. if the d cs-control functionality is not desired, then the csr input can be hardwired to ground, in which case the setup time requirement for d cs would be the same as for the other d data inputs. the SSTU32864 is available in the lfbga96 package.
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 2 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. features n con?gurable register supporting ddr2 registered dimm applications n con?gurable to 25-bit 1:1 mode or 14-bit 1:2 mode n controlled output impedance drivers enable optimal signal integrity and speed n exceeds jesd82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) n supports up to 450 mhz clock frequency of operation n optimized pinout for high-density ddr2 module design n chip-selects minimize power consumption by gating data outputs from changing state n supports sstl_18 data inputs n differential clock (ck and ck) inputs n supports lvcmos switching levels on the control and reset inputs n single 1.8 v supply operation n available in 96-ball, 13.5 5.5 mm, 0.8 mm ball pitch lfbga package 3. ordering information table 1: ordering information t amb =0 cto+70 c. type number package name description solder process version SSTU32864ec/g lfbga96 plastic low pro?le ?ne-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm pb-free (snagcu solder ball compound) sot536-1 SSTU32864ec lfbga96 plastic low pro?le ?ne-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm snpb solder ball compound sot536-1
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 3 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. pinning information 4.1 pinning fig 1. ball mapping; 1:1 register (c0 = 0, c1 = 0); top view. dcke n.c. v ref v dd qcke dnu 123456 d2 d15 gnd gnd q2 q15 a b d3 d16 v dd v dd q3 q16 c dodt n.c. gnd gnd qodt dnu d d5 d17 v dd v dd q5 q17 e d6 d18 gnd gnd q6 q18 f n.c. reset v dd v dd c1 c0 g ck dcs gnd gnd qcs dnu h ck csr v dd v dd zoh zol j d8 d19 gnd gnd q8 q19 k d9 d20 v dd v dd q9 q20 l d10 d21 gnd gnd q10 q21 m d11 d22 v dd v dd q11 q22 n d12 d23 gnd gnd q12 q23 p d13 d24 v dd v dd q13 q24 r d14 d25 v ref v dd q14 q25 t 002aaa955
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 4 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 2. ball mapping; 1:2 register a (c0 = 0, c1 = 1); top view. fig 3. ball mapping; 1:2 register b (c0 = 1, c1 = 1); top view. dcke n.c. v ref v dd qckea qckeb 123456 d2 dnu gnd gnd q2a q2b a b d3 dnu v dd v dd q3a q3b c dodt n.c. gnd gnd qodta qodtb d d5 dnu v dd v dd q5a q5b e d6 dnu gnd gnd q6a q6b f n.c. reset v dd v dd c1 c0 g ck dcs gnd gnd qcsa h ck csr v dd v dd zoh zol j d8 dnu gnd gnd q8a q8b k d9 dnu v dd v dd q9a q9b l d10 dnu gnd gnd q10a q10b m d11 dnu v dd v dd q11a q11b n d12 dnu gnd gnd q12a q12b p d13 dnu v dd v dd q13a q13b r d14 dnu v ref v dd q14a q14b t 002aaa956 qcsb d1 n.c. v ref v dd q1a q1b 123456 d2 dnu gnd gnd q2a q2b a b d3 dnu v dd v dd q3a q3b c d4 n.c. gnd gnd q4a q4b d d5 dnu v dd v dd q5a q5b e d6 dnu gnd gnd q6a q6b f n.c. reset v dd v dd c1 c0 g ck dcs gnd gnd qcsa h ck csr v dd v dd zoh zol j d8 dnu gnd gnd q8a q8b k d9 dnu v dd v dd q9a q9b l d10 dnu gnd gnd q10a q10b m dodt dnu v dd v dd qodta qodtb n d12 dnu gnd gnd q12a q12b p d13 dnu v dd v dd q13a q13b r dcke dnu v ref v dd qckea qckeb t 002aaa957 qcsb
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 5 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4.2 pin description [1] con?gurations: data inputs = d2, d3, d5, d6, d8-d25 when c0 = 0 and c1 = 0. data inputs = d2, d3, d5, d6, d8-d14 when c0 = 0 and c1 = 1. data inputs = d1-d6, d8-d10, d12, d13 when c0 = 1 and c1 = 1. [2] con?gurations: data outputs = q2, q3, q5, q6, q8-q25 when c0 = 0 and c1 = 0. data outputs = q2, q3, q5, q6, q8-q14 when c0 = 0 and c1 = 1. data outputs = q1-q6, q8-q10, q12, q13 when c0 = 1 and c1 = 1. table 2: pin description symbol description electrical characteristics gnd ground ground input v dd power supply voltage 1.8 v nominal v ref input reference voltage 0.9 v nominal z oh reserved for future use input z ol reserved for future use input ck positive master clock input differential input ck negative master clock input differential input c0, c1 con?guration control inputs lvcmos inputs reset asynchronous reset input. resets registers and disables v ref data and clock differential-input receivers. lvcmos input csr, d cs chip select inputs. disables data outputs switching when both inputs are high (see table note [1] ). sstl_18 input d[1:25] data inputs. clocked in on the crossing of the rising edge of ck and the falling edge of ck. sstl_18 input dodt the outputs of this register will not be suspended by d cs and csr control. sstl_18 input dcke the outputs of this register will not be suspended by d cs and csr control. sstl_18 input q[1:25] the outputs that are suspended by d cs and csr control (see table note [2] ). 1.8 v cmos q cs data outputs that will not be suspended by d cs and csr control. 1.8 v cmos qodt data outputs that will not be suspended by d cs and csr control. 1.8 v cmos qcke data outputs that will not be suspended by d cs and csr control. 1.8 v cmos n.c. no-connect. ball present but no internal connection to the die. - dnu do-not-use. ball internally connected to the die which should be left open-circuit. -
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 6 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. functional description (1) disabled in 1:1 con?guration. fig 4. logic diagram, 1:2 mode (positive logic). 002aaa954 1d r 1d r 1d r qckea qckeb (1) qodta qodtb (1) qcsa qcsb (1) c1 c1 c1 csr dcs dodt dcke d1 0 1 1d r q1a q1b (1) c1 to other channels ck v ref ck reset
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 7 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. h high voltage level l low voltage level high-to-low transition - low-to-high transition x dont care table 3: function table (each ?ip-?op) inputs outputs reset d cs csr ck ck dn, dodt, dcke q q q hll - lll l hll - hhl h h l l l or h l or h x qo qo qo hlh - lll l hlh - hhl h h l h l or h l or h x qo qo qo hhl - llhl hhl - hhh h h h l l or h l or h x qo qo qo hhh - lqoh l hhh - hqoh h h h h l or h l or h x qo qo qo l x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating ll l
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 8 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. limiting values [1] stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operatin g conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] the input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. [3] this value is limited to 2.5 v maximum. 7. recommended operating conditions [1] the reset and cn inputs of the device must be held at valid logic levels (not ?oating) to ensure proper device operation. the differential inputs must not be ?oating, unless reset is low. table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +2.5 v v i receiver input voltage [2] , [3] - 0.5 +2.5 v v o driver output voltage [2] , [3] - 0.5 v dd + 0.5 v i ik input clamp current v i < 0 v or v i >v dd - 50 ma i ok output clamp current v o < 0 v or v o >v dd - 50 ma i o continuous output current 0 < v o < v dd - 50 ma i ccc continuous current through each v dd or gnd pin - 100 ma t stg storage temperature - 65 +150 c table 5: recommended operating conditions symbol parameter conditions min nom max unit v dd supply voltage 1.7 - 1.9 v v ref reference voltage 0.49 v dd 0.50 v dd 0.51 v dd v v tt termination voltage v ref - 40 mv v ref v ref +40mv v v i input voltage 0 - v dd v v ih ac high-level input voltage data inputs, csr v ref + 250 mv - - v v il ac low-level input voltage data inputs, csr - - v ref - 250 mv v v ih dc high-level input voltage data inputs, csr v ref + 125 mv - - v v il dc low-level input voltage data inputs, csr - - v ref - 125 mv v v ih high-level input voltage reset, cn 0.65 v dd -v dd v v il low-level input voltage reset, cn - - 0.35 v dd v v icr common mode input voltage range ck, ck 0.675 - 1.125 v v id differential input voltage ck, ck 600 - - mv i oh high-level output current - - - 8ma i ol low-level output current - - 8 ma t amb operating ambient temperature in free air 0 - +70 c
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 9 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. static characteristics table 6: dc electrical characteristics over recommended operating conditions, unless otherwise noted. voltages are referenced to gnd (groun d=0v). t amb =0 cto+70 c. symbol parameter conditions min typ max unit v oh high-level output voltage i oh = - 6 ma; v dd = 1.7 v 1.2 - - v v ol low-level output voltage i ol = 6 ma; v dd = 1.7 v - - 0.5 v i i input current all inputs; v i =v dd or gnd; v dd = 1.9 v - 5- +5 m a i dd static standby current reset = gnd; i o = 0 ma; v dd = 1.9 v - - 100 m a static operating current reset = v dd ; i o = 0 ma; v dd = 1.9 v; v i =v ih(ac) or v il(ac) - - 40 ma i ddd dynamic operating current, clock only reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. i o = 0 ma; v dd = 1.9 v -16- m a / mhz dynamic operating current, per each data input, 1:1 mode reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. i o = 0 ma; v dd = 1.9 v -11- m a / mhz dynamic operating current, per each data input, 1:2 mode reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. i o = 0 ma; v dd = 1.9 v -19- m a / mhz c i input capacitance, data inputs, csr v i =v ref 250 mv; v dd = 1.8 v 2.5 - 3.5 pf input capacitance, ck and ck v icr = 0.9 v; v id = 600 mv; v dd = 1.8 v 2-3pf input capacitance, reset v i =v dd or gnd; v dd = 1.8 v 2 - 4 pf
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 10 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. dynamic characteristics [1] this parameter is not necessarily production tested. [2] data inputs must be active below a minimum time of t act (max) after reset is taken high. [3] data and clock inputs must be held at valid levels (not ?oating) a minimum time of t inact (max) after reset is taken low. [1] includes 350 ps of test-load transmission line delay. [2] this parameter is not necessarily production tested. [1] difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate). table 7: timing requirements over recommended operating conditions; v dd = 1.8 v 0.1 v; t amb =0 cto+70 c; unless otherwise noted. see figures 5 through 10 . symbol parameter conditions min typ max unit f clock clock frequency - - 450 mhz t w pulse duration, ck, ck high or low 1--ns t act differential inputs active time [1] , [2] --10ns t inact differential inputs inactive time [1] , [3] --15ns t su set-up time d cs before ck - , ck , csr high 0.7 - - ns d cs before ck - , ck , csr low 0.5 - - ns csr, odt, cke, and data before ck - , ck 0.5 - - ns t h hold time d cs, csr, odt, cke, and data after ck - , ck 0.5 - - ns table 8: switching characteristics over recommended operating conditions; v dd = 1.8 v 0.1 v; t amb =0 cto+70 c; class i, v ref =v tt =v dd 0.5 and cl = 10 pf (unless otherwise noted. see figures 5 through 10 . symbol parameter conditions min typ max unit f max maximum input clock frequency 450 - - mhz t pdm propagation delay clock to output [1] 1.41 - 1.8 ns t pdmss propagation delay, simultaneous switching clock to output [1] , [2] - - 2.0 ns t phl propagation delay reset to output - - 3 ns table 9: output edge rates over recommended operating conditions, unless otherwise noted. v dd = 1.8 v 0.1 v symbol parameter conditions min typ max unit dv/dt_r rising edge slew rate 1 - 4 v/ns dv/dt_f falling edge slew rate 1 - 4 v/ns dv/dt_ d [1] absolute difference between dv/dt_r and dv/dt_f - - 1 v/ns
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 11 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. test information 10.1 test circuit all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20%, unless otherwise speci?ed. the outputs are measured one at a time with one transition per measurement. (1) c l includes probe and jig capacitance. fig 5. load circuit. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. fig 6. voltage and current waveforms; inputs active and inactive times. v id = 600 mv v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 7. voltage waveforms; pulse duration. r l = 100 w r l = 1000 w v dd t l = 50 w ck inputs ck ck out dut test point 002aaa371 test point t l = 350 ps, 50 w r l = 1000 w c l = 30 pf see note (1) lvcmos reset 10% i dd (see note) t inact v dd v dd /2 t act 90% 0 v 002aaa372 v dd /2 v icr v icr v ih v il input t w v id 002aaa373
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 12 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. v id = 600 mv v ref =v dd /2 v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 8. voltage waveforms; set-up and hold times. t plh and t phl are the same as t pd . fig 9. voltage waveforms; propagation delay times. t plh and t phl are the same as t pd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 10. voltage waveforms; propagation delay times. t su v ih v il v id t h ck ck input v ref v ref v icr 002aaa374 v oh v ol output t plh 002aaa375 v tt v icr v icr t phl ck ck v i(p-p) t phl 002aaa376 lvcmos reset input output v tt v dd /2 v ih v il v oh v ol
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 13 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2 output slew rate measurement v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20 %, unless otherwise speci?ed. (1) c l includes probe and jig capacitance. fig 11. load circuit, high-to-low slew measurement. fig 12. voltage waveforms, high-to-low slew rate measurement. (1) c l includes probe and jig capacitance. fig 13. load circuit, low-to-high slew measurement. fig 14. voltage waveforms, low-to-high slew rate measurement. c l = 10 pf see note (1) v dd out dut test point r l = 50 w 002aaa377 v oh v ol output 80% 20% dv_f dt_f 002aaa378 c l = 10 pf see note (1) out dut test point r l = 50 w 002aaa379 v oh v ol 80% 20% dv_r dt_r output 002aaa380
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 14 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. package outline fig 15. lfbga96 package outline (sot536-1). 0.8 a 1 b a 2 unit d y e references outline version european projection issue date 00-03-04 03-02-05 iec jedec jeita mm 1.5 0.41 0.31 1.2 0.9 5.6 5.4 y 1 13.6 13.4 0.51 0.41 0.1 0.2 e 1 4 e 2 12 dimensions (mm are the original dimensions) sot536-1 e 0.15 v 0.1 w 0 5 10 mm scale sot536-1 lfbga96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm a max. a a 2 a 1 detail x e e x d e a b c d e f h g j k l m p n r t 246 135 b a e 2 e 1 ball a1 index area ball a1 index area y y 1 c b c a c c b ? v m ? w m 1/2 e 1/2 e
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 15 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 12.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 16 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 12.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 10: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications objective data rev. 01 12 july 2004 17 of 19 9397 750 13339 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 13. revision history table 11: revision history rev date cpcn description 01 20040712 - objective data (9397 750 13339)
9397 750 13339 philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data rev. 01 12 july 2004 18 of 19 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 14. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 16. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 july 2004 document order number: 9397 750 13339 contents philips semiconductors SSTU32864 1.8 v con?gurable registered buffer for ddr2 rdimm applications 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 4.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 functional description . . . . . . . . . . . . . . . . . . . 6 6 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 recommended operating conditions. . . . . . . . 8 8 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 9 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10 test information . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1 test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.2 output slew rate measurement. . . . . . . . . . . . 13 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 12.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 12.5 package related soldering information . . . . . . 16 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 14 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 15 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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